This invention relates to a cellular trench-gate FET and to a method of forming the same.
A previous application of the present applicant, WO 01/08226, the contents of which are incorporated herein by reference, describes an edge termination in a cellular trench-gate MOSFET device. It is known to have a cellular trench-gate MOSFET having a semi-conductor body having an array of transistor cells, in which the cells are bounded by a pattern of trenches lined with dielectric material within the array and around the perimeter of the array. The array trenches extend from a surface of the body through a body region of a first conductivity type into an underlying drain drift region of an opposite second conductivity type. The dielectric material in the array trenches provides a gate dielectric layer adjacent to the body region. A gate electrode on the gate dielectric layer provides a trench-gate in the array trenches, for controlling current flow in a conduction channel from a source region at the surface of the body to the drain drift region in a conductive state of the transistor. A depletion layer is formed in the drain drift region from the p-n junction with the body region and from the trench-gate in a blocking state of the transistor. Premature breakdown of these transistors can occur at high field points in the depletion layer, especially at the perimeter of the array.
WO 01/08226 addressed the problem of premature breakdown of such transistors by providing a field plate on dielectric material in a perimeter trench. The dielectric material formed a thicker dielectric layer than the gate dielectric layer in the array trenches. The field plate was connected to the source or trench-gate of the transistor and acted inwardly towards the cellular array rather than outwardly towards the body perimeter, because of its presence on the inside wall of the trench without acting on any outside wall. That arrangement reduced the risk of premature breakdown that can occur at high field points in the depletion layer, especially at the perimeter of the cellular array.
It is an object of the present invention to make further improvement in relation to breakdown voltage beyond those achieved by WO 01/08226.
According to a first aspect of the present invention a cellular trench-gate field-effect transistor comprises a semiconductor body having an array of transistor cells, the cells being bounded by a pattern of perimeter trenches lined with dielectric material around the perimeter of the array, the perimeter trench having an inner wall closer to an active area of the transistor and an outer wall closer to the edge of the transistor, characterised in that each of said inner and outer walls has a field plate located on the dielectric material and the field plate on the inner wall of the perimeter trench is connected to a source or trench-gate of the transistor.
The field plate on the outer wall may be floating in potential.
The breakdown voltage of the transistor is thereby beneficially increased.
The perimeter trench may include dielectric material between the field plates on the inner and outer walls.
Each of said perimeter trenches has a field plate on said inner wall, and may have a field plate on said outer wall.
Preferably, the transistor is a trench-gate MOSFET. Preferably, the transistor is manufactured by a self-aligned process, giving a self-aligned transistor.
The field plates are preferably formed of polysilicon or may be formed of metal.
The perimeter trenches may have thicker dielectric than gate dielectric in an active area of the transistor.
Preferably, the transistor cells are hexagon cells or square cells. Preferably, the perimeter trenches are in the shape of hexagon cells or square cells.
Preferably, the inner wall field plate is connected to the trench gate.
According to a second aspect of the present invention a method manufacturing a trench-gate field-effect transistor comprises:
forming an array of transistor cells on a semiconductor body;
forming a pattern of perimeter trenches around the perimeter of the array of transistor cells;
lining the perimeter trenches with dielectric material;
characterised by
forming an inner field plate on an inner wall of the perimeter trench closer to the array and forming an outer field plate on an outer wall of the perimeter trench closer to an edge of the transistor; and
connecting the inner field plate to a source or trench-gate of the transistor.
Preferably, steps d) and e) are performed in a self-aligned manner.
Preferably, step d) is performed by depositing a conductive layer, which may be polysilicon, in the perimeter trenches preferably followed by etching said conductive layer anisotropically to remove the conductive layer from the bottom of the perimeter trench and from the upper face of the pattern of perimeter trenches.
The conductive layer is thereby advantageously left on the sidewalls of the perimeter trench.
Material for the trench-gate and trench connection layer may be deposited in the perimeter trenches and over an upper face of the pattern of perimeter trenches and may be subsequently etched away from the perimeter trenches to be replaced with a conductive layer, which is preferably thinner than the previous layer, that provides the inner and outer field plates.
All of the features disclosed herein may be combined with any of the above aspects in any combination.